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Rev 1; 2/09
Dual Delta-Sigma Modulator and Encoder
General Description
The DS8102 is a stand-alone, dual-channel, deltasigma modulator that converts measurements from two differential analog input pairs into a Manchester-encoded output bit stream that can be processed by a companion microcontroller such as the MAXQ3108. One channel operates at a fixed 1x gain, while the other operates at a pin-selectable gain of 1x, 4x, 16x, or 32x. The DS8102 includes an internal power-supply monitor, on-board voltage reference, and low-power oscillator to reduce the number of external components required for data acquisition. The Manchester-encoded output from the DS8102 combines pulse-density-modulated measurement values from both differential input channels with a synchronization bit stream and is transmitted over a single pin. This transmission scheme is ideal for split voltage domain applications where the DS8102 and other "hot"side components must be electrically isolated from "cold" low-voltage components such as a companion microcontroller. In this type of application, the DS8102 can be capacitively coupled to a companion microcontroller with only two connection points required (MNOUT and DGND). The MAXQ3108 dual-core microcontroller, which includes specialized Manchester bit-stream decoding inputs and sinc3 filters, is specifically designed to act as a companion microcontroller for up to three DS8102 devices. This configuration, which supports up to six differential analog input channels, is well suited for three-phase electricity-metering applications.
Features
Dual Delta-Sigma 2nd-Order Modulators Channel 0: Pin-Selectable Gain of 1x, 4x, 16x, or 32x Channel 1: Fixed Gain of 1x Selectable Internal or External Voltage Reference Manchester-Encoded Bit Stream Output Includes Synchronization Bits to Allow Clock Recovery Single-Pin Transmission Scheme Simplifies Electrical Isolation Using Capacitive Coupling Selectable Internal or External Clock Source Integrated Low-Power 8MHz Oscillator Operating Mode Active Mode (8MHz, VDD = 3.6V): 3.5mA
DS8102
Ordering Information
PART DS8102+ TEMP RANGE -40C to +85C PIN-PACKAGE 16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
DGND AGND VREF AN1AN1+ AN0AN0+ VDD 1 2 3 4 5 6 7 8 DS8102
+
Applications
Single-Phase Electricity Metering Three-Phase Electricity Metering Power-Line Conditioning Electrochemical and Optical Sensors Industrial Control Data-Acquisition Systems and Data Loggers
16 15 14 13 12 11 10 9
VDD APDREF RST MNOUT CLKIO G1 G0 CLKSEL
TSSOP
Typical Operating Circuit appears at end of data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual Delta-Sigma Modulator and Encoder DS8102
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD Relative to DGND.............-0.3V to +4.0V Voltage Range on VDD Relative to AGND .............-0.3V to +4.0V Voltage Range on AGND Relative to DGND .........-0.3V to +0.3V Voltage Range on Any Pin Relative to DGND Except AN0+, AN0-, and AN1+, AN1- ...............-0.3V to +4.0V Voltage Range on AN0+, AN0-, AN1+, and AN1Relative to AGND ...............................................-4.0V to +4.0V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V, TA = -40C to +85C, fCLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage Power-Fail Reset Voltage Active VDD Current Shutdown (Power-Down) VDD Current Input Low Voltage Input High Voltage Output Low Voltage (CLKIO, MNOUT) Output High Voltage (CLKIO, MNOUT) Input/Output Pin Capacitance Input Leakage Current (All Inputs) CLOCK SOURCE External Clock Input Frequency External Clock Input Period External Clock Input Duty Cycle Internal Oscillator Output Frequency SYMBOL VDD VRST IDD I STOP VIL VIH VOL VOH CIO IL f XCLK CLKSEL = 1 I OL = 4mA I OH = -4mA (Note 3) -100 DC 125 40 7.5 47.8 8.0 49.1 60 8.5 49.7 Monitors VDD Normal operation RST = 0 or VDD < VRST DGND 0.7 x VDD DGND VDD - 0.4 15 +100 8 CONDITIONS MIN VRST 2.7 TYP (Note 2) 3.3 2.8 3.5 2 0.3 x VDD VDD 0.4 MAX 3.6 2.99 5.0 UNITS V V mA nA V V V V pF nA MHz ns % MHz %
t XCLK-CLCL CLKSEL = 1 t XCLK-DUTY CLKSEL = 1 f ICLK CLKSEL = 0 CLKSEL = 0
Internal Oscillator Output Duty t ICLK-DUTY Cycle ANALOG-TO-DIGITAL CONVERTER AFE Warmup Delay Reference Buffer Warmup Delay tWU1 tWU2
f ICLK = 8MHz (Notes 1, 4) f ICLK = 8MHz (Notes 1, 5) OSR = 32 16 19 22 24 0.01 OSR = 64 OSR = 128 OSR = 256
1.02 7.17
ms ms
Decimator Output (Note 6)
Bits
Integral Nonlinearity Offset Error
INL
(Notes 1, 6) Gain = 1 (Note 6)
%FSR 1.4 mV
2
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Dual Delta-Sigma Modulator and Encoder
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V, TA = -40C to +85C, fCLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP (Note 2) MAX UNITS
DS8102
ANALOG-TO-DIGITAL CONVERTER DYNAMIC SPECIFICATIONS DC Power-Supply Rejection Ratio PSRR VDD = 3.0V to 3.6V, AN0+ = AN0- = AGND, 100mV ripple on VDD VDD = 3.6V, gain = 1, AN0 = 500mV P-P, sinewave at 62.5Hz VDD = 3.6V, gain = 32, AN0 = 20mV P-P, sinewave at 62.5Hz VDD = 3.6V, gain = 32, AN0 = 20mV P-P, sinewave at 62.5Hz AN0+, AN0-, AN1+, and AN1- to AGND Gain = 1 Input Sampling Capacitance (Note 1) Input Sampling Rate Input Impedance to AGND for 8MHz (Note 8) CIN Gain = 4 Gain = 16 Gain = 32 fS Clock at 8MHz (Note 7) Gain = 1 Gain = 4 Gain = 16 Gain = 32 Gain = 1 Differential Input Impedance for 8MHz (Note 9) Input Bandwidth (-3dB) External Reference Input Voltage External Reference Input Sampling Capacitance Reference Input Sampling Rate INTERNAL REFERENCE Reference Output Voltage 1.24 V Reference Output Temperature 30 ppm/C Coefficient Note 1: Specifications to -40C are guaranteed by design and not production tested. Note 2: Typical values are not guaranteed. These values are measured at room temperature, VDD = 3.3V. Note 3: These numbers are guaranteed by design and are not tested. Note 4: Calculated as tWU1 = 1/fICLK x 8192. Note 5: Calculated as tWU2 = 1/fICLK x 57,344. Note 6: Parameter specifications are based upon the presence of an external cubic sinc filter (as implemented in the MAXQ3108) for generating full ADC output codewords. Note 7: fS = fCLK/12. fCLK is the system clock frequency. Note 8: This is a function of input sampling capacitance (CIN) and sampling frequency, and can be approximated as 6/(fCLK x CIN). Note 9: ZIN (differential) = 2 x ZIN (single-ended). fS VREF 1.2 Gain = 4 Gain = 16 Gain = 32 -1 1 4 16 32 0.667 750 187 47 23.4 1500 375 94 46.9 7 1.25 2 0.67 1 1.3 kHz V pF MHz k k MHz pF 70 70 95 85 dB 85 -95 -70 dB dB
Signal-to-Noise Ratio
SINAD
Total Harmonic Distortion THD (to 21st Harmonic) ANALOG-TO-DIGITAL CONVERTER INPUTS Input Voltage Range
+1
V
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Dual Delta-Sigma Modulator and Encoder DS8102
Pin Description
PIN 1 2 3 4 5 6 7 8, 16 9 NAME DGND AGND VREF AN1AN1+ AN0AN0+ VDD CLKSEL Digital Ground Analog Ground Reference Voltage Input/Output. When APDREF = 0, the buffered internal voltage reference is driven on this pin as an output and can be used by other devices. When APDREF = 1, an external voltage reference must be provided on this pin. Negative Input for Differential Analog Input Channel 1 Positive Input for Differential Analog Input Channel 1 Negative Input for Differential Analog Input Channel 0 Positive Input for Differential Analog Input Channel 0 Digital and Analog Power Supply Clock Select Input. When CLKSEL = 0, the DS8102 uses its internal 8MHz oscillator as a clock source. When CLKSEL = 1, the DS8102 operates from an external clock source (which must be provided at CLKIO). Gain Select Input 0. This pin, along with G1, is used to select the gain setting for differential analog input channel 0. Gain Select Input 1. This pin, along with G0, is used to select the gain setting for differential analog input channel 0. Clock Input/Output. When CLKSEL = 0 (internal clock selected), the internal 8MHz clock is output on this pin and can be used by external devices. When CLKSEL = 1 (external clock selected), an external clock must be provided on this pin. Manchester Encoder Output. This output pin provides a Manchester-encoded bit stream containing output bits from both modulators interleaved with an alternating synchronization bit. Reset. This input pin can be used to force the DS8102 into a shutdown (low-power) state by driving RST = 0. If the external reset function is not used, this pin must be connected to VDD for proper operation. An RC circuit is not required on this pin for power-up, as this function is provided internally. Analog Power-Down Reference. This input pin controls whether the internal voltage reference is enabled. If APDREF = 0, the internal voltage reference is enabled and the voltage reference level is driven out on VREF. If APDREF = 1, the internal voltage reference is disabled and an external voltage reference must be provided on VREF. FUNCTION
10 11
G0 G1
12
CLKIO
13
MNOUT
14
RST
15
APDREF
4
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Dual Delta-Sigma Modulator and Encoder
Functional Diagram
APDREF RST
DS8102
INTERNAL REFERENCE VREF
REFERENCE BUFFER
8MHz OSCILLATOR
CLKSEL CLKIO
AN1+ AN1-
1x
INTEGRATORS/ COMPARATOR
DS8102
DELTA-SIGMA MODULATOR 1x, 4x, 16x, 32x
MANCHESTER ENCODER
MNOUT
AN0+ AN0-
INTEGRATORS/ COMPARATOR POWER MONITOR
DELTA-SIGMA MODULATOR G1 G0 AGND DGND
VDD
Detailed Description
Operating Modes
The DS8102 has two operating modes: shutdown (or power-down) mode and active mode.
1) Drive the RST line on the DS8102 low to force the DS8102 into shutdown mode. 2) Enter stop mode. Both the companion microcontroller and the DS8102 are now in their lowest current consumption modes. 3) Exit stop mode. 4) Drive the RST line on the DS8102 high to return the DS8102 to active mode. Note: The RST line on the DS8102 does not include a pullup. This means that if the RST line is not driven by a companion microcontroller, RST must be connected to VDD for proper operation. RST cannot be left unconnected. While the DS8102 is in shutdown mode, the levels on the configuration input pins (APDREF, CLKSEL, G1, and G0) can be changed if they are being driven by a companion microcontroller instead of hardwired to VDD or DGND. However, once the DS8102 enters active mode, the levels on these pins must remain static for proper operation.
Shutdown Mode In shutdown mode, the DS8102 is in an inactive state and consumes a minimal amount of current. No analogto-digital conversion or encoding is performed, and the internal 8MHz oscillator and internal voltage reference are disabled. An integrated power-supply monitor holds the DS8102 in shutdown mode whenever VDD VRST. Additionally, the RST pin can be driven low by an external companion microcontroller (such as the MAXQ3108) to force the DS8102 to remain in shutdown mode, regardless of the supply level at VDD. This is useful in nonisolated configurations (when a power supply is shared between the DS8102 and the companion microcontroller) to reduce the current consumption of the entire system. In this scenario, the companion microcontroller would perform this sequence of actions when entering stop mode:
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5
Dual Delta-Sigma Modulator and Encoder
Once the power supply is at an acceptable level (V DD > V RST ) and the RST line is driven high, the DS8102 exits shutdown mode. However, a warmup sequence must then be completed before analog-todigital conversion and Manchester encoding begins. The length of this sequence depends on the internal/external voltage reference mode (controlled by the APDREF pin). If the external voltage reference is selected (APDREF = 1), the following actions are performed: 1) Upon exit from shutdown mode (VDD > VRST and RST = 1), the 8MHz oscillator is started. 2) The DS8102 delays for 16 cycles of the 8MHz oscillator. This allows the 8MHz oscillator to warm up. 3) The analog front-end (AFE) is enabled. 4) The DS8102 delays for 8192 cycles of the 8MHz oscillator. This allows the AFE to warm up. 5) If CLKSEL = 1, the 8MHz oscillator is disabled at this point and the DS8102 switches to the external clock source provided at CLKIO. 6) Both modulator channels are enabled, and the DS8102 begins performing conversions using the external voltage reference. If the internal voltage reference is selected (APDREF = 0), the followings actions are performed: 1) Upon exit from shutdown mode (VDD > VRST and RST = 1), the 8MHz oscillator is started. 2) The DS8102 delays for 16 cycles of the 8MHz oscillator. This allows the 8MHz oscillator to warm up. 3) The AFE is enabled. 4) The DS8102 delays for 8192 cycles of the 8MHz oscillator. This allows the AFE to warm up. 5) The internal voltage reference is enabled. 6) The DS8102 delays for an additional 57,344 cycles of the 8MHz oscillator. This allows the internal reference to warm up. 7) If CLKSEL = 1, the 8MHz oscillator is disabled at this point and the DS8102 switches to the external clock source provided at CLKIO. 8) Both modulator channels are enabled, and the DS8102 begins performing conversions using the internal voltage reference. Even if the external clock has been selected by setting CLKSEL = 1, the internal 8MHz oscillator is still used to control the warmup sequence. Once the warmup sequence has completed, the internal 8MHz oscillator is disabled if CLKSEL = 1.
6
Active Mode In active mode, the AFE and delta-sigma modulators on the DS8102 are enabled, and the DS8102 converts and outputs samples over the Manchester-encoded output (MNOUT) at a rate determined by either the internal 8MHz oscillator (if CLKSEL = 0) or the external clock input at CLKIO (if CLKSEL = 1). If RST is driven low or if VDD drops below the VRST level, the DS8102 enters shutdown mode immediately and must go through the warmup sequence again (once VDD > VRST and RST = 1) to return to active mode.
DS8102
Configuration Inputs
The input pins G0, G1, APDREF, and CLKSEL are configuration inputs for the DS8102 that determine its operating mode, including: * Clock selection--internal or external * Voltage reference--internal or external * Gain setting for analog input channel 0--1x, 4x, 16x, or 32x These pins must be set to a valid level for proper operation; they cannot be left disconnected. If any of the configuration inputs are driven by a companion microcontroller (as opposed to being statically connected to VDD or DGND), the inputs can only be changed when the DS8102 is in shutdown mode.
Channel 0 Gain Selection
Configuration input pins G0 and G1 are used to select the gain setting for analog input channel 0. The available gain configurations are 1x, 4x, 16x, and 32x. The effective input voltage range scales downward proportionally with each increased gain selection. For example, full-scale output at gain = 1x occurs when AN0+ is 2V higher than AN0-. However, with the gain setting at 4x, the output reaches full scale when AN0+ is only 500mV higher than AN0-. Table 1 lists the gain configuration settings available for channel 0. The levels at G0 and G1 should be set when the DS8102 is in shutdown mode.
Table 1. Modulator 0 Gain Settings
G1 PIN 0 0 1 1 G0 PIN 0 1 0 1 GAIN 1x 4x 16x 32x
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Dual Delta-Sigma Modulator and Encoder
Internal/External Voltage Reference Selection
The configuration pin APDREF selects whether the DS8102 uses its internal voltage reference or an external voltage reference provided at VREF when performing conversions. If the internal voltage reference is selected, the internal reference is buffered and driven out at VREF, and can be used by external devices if desired. Table 2 summarizes the modes of operation for the DS8102 based on the APDREF input. The level at APDREF should be set when the DS8102 is in shutdown mode. occurs halfway through the bit time slot. As shown in Figure 1, the Manchester-encoded bitstream output on MNOUT contains three interleaved bit streams. These bit streams, in the order that they are output, are as follows: 1) SYNC--Synchronization bit stream containing alternating 0s and 1s. 2) CHAN0--Pulse-density-modulated output from analog channel 0. 3) CHAN1--Pulse-density-modulated output from analog channel 1. Both modulator outputs are always included in the bit stream, even if only one of them is being used by the application. This means that the maximum bit-rate output for either modulator channel over MNOUT is fCLK/12 as shown in Figure 1.
DS8102
Internal/External Clock Selection
The configuration input pin CLKSEL selects whether the DS8102 uses the internal 8MHz oscillator or an external clock (provided at CLKIO) when performing conversions. If the internal 8MHz oscillator is selected, the internal clock is driven out at CLKIO and can be used by external devices if desired. Table 3 summarizes the modes of operation for the DS8102 based on the CLKSEL input. The level at CLKSEL should be set when the DS8102 is in shutdown mode.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified.
Manchester Encoder
Once the DS8102 enters active mode, it begins generating a Manchester-encoded bit stream on the MNOUT pin. This bit stream is output at a rate equal to the selected clock frequency divided by 4, so, for example, if the internal 8MHz oscillator is selected as the DS8102 clock source, a new bit is output on MNOUT approximately every 500ns. Bit values are encoded as either low-to-high transitions (for bit values of 1) or high-to-low transitions (for bit values of 0). The transition from low-to-high or high-to-low
Offset Error
For an ideal converter, the first transition occurs at 0.5 LSB above zero. Offset error is the amount of deviation between the measured first transition point and the ideal point.
Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) is the ratio of changes in the power supply (V) to changes in the converter output (V). It is typically measured in decibels.
Table 2. Voltage Reference Selection and Operating Modes
RST PIN 0 1 1 APDREF PIN X 0 1 Shutdown. Operation using internal voltage reference (VREF output buffer enabled). Operation using external voltage reference (VREF output buffer disabled). DS8102 MODE
Table 3. Clock Source Selection
CLKSEL PIN 0 1 DS8102 CLOCK SOURCE Internal 8MHz oscillator External clock (provided at CLKIO) CLKIO PIN MODE Output: Drives out 8MHz clock. Input: Accepts external clock.
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7
Dual Delta-Sigma Modulator and Encoder DS8102
1 1 CLKIO 0 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
CHAN0
CHAN1
CHAN0
CHAN1
CHAN0
CHAN1
CHAN0
1 MNOUT
0
0
0
0
1
1
1
0
0
1
Figure 1. Manchester Encoder Output Example
Typical Operating Circuit
DC POWER SUPPLY 1 2 3 4 5 6 7 8 DGND AGND VREF AN1AN1+ AN0AN0+ VDD DS8102 VDD APDREF RST MNOUT CLKIO G1 G0 CLKSEL 16 15 14 13 12 11 10 9 ISOLATION CAPACITORS COMPANION C MNIN+ MNIN-
VDD
DGND
VOLTAGEDIVIDER AC LINE OUT CURRENT SHUNT AC NEUTRAL OUT
LINE SUPPLY AC LINE IN AC NEUTRAL IN
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 TSSOP PACKAGE CODE U16+2 DOCUMENT NO. 21-0066
8
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CHAN1 1
SYNC
SYNC
SYNC
SYNC
Dual Delta-Sigma Modulator and Encoder
Revision History
REVISION NUMBER 0 REVISION DATE 1/09 Initial release. Changed the part number in the Ordering Information table. In the Electrical Characteristics table, changed fXCLK(MAX) from 12MHz to 8MHz; changed tXCLK-CLCL(MIN) from 83ns to 125ns; changed the Offset Error parameter from 1.4mV (min) to 1.4mV (max); added new conditions and note and changed 1.33MHz (typ) to 0.667MHz (typ) for the Input Sampling Rate parameter. Corrected the reference from CLKSEL to APDREF in the Internal/External Voltage Reference Selection section; corrected the reference from APDREF to CLKSEL in the Internal/External Clock Selection section. DESCRIPTION PAGES CHANGED -- 1
DS8102
2, 3
1
2/09
7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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